Pomegra
Celera Semiconductor has secured $30 million from sole investor Maverick Silicon to scale its AI-driven digital twin platform for analog chip design, which cuts development time to a tenth of traditional methods.
Key Takeaways
- Maverick Silicon funds the full $30M Series B, bringing Celera's total raised to $50M in 12 months.
- Celera's Nesto™ platform uses digital twins of analog functions, delivering full-custom ICs in 10% of the time conventional workflows require.
- Proceeds accelerate engineering expansion in California and Portugal following Celera's June 2026 acquisition of SiliconGate.
Lead
California-based Celera Semiconductor closed a $30 million Series B on August 25, 2026, with Maverick Silicon as the sole backer. It follows a $20 million Series A from the same investor in August 2025, bringing total capital raised to $50 million in 12 months. Celera builds AI-powered design automation for the custom analog integrated circuit market - a segment notorious for development cycles that stretch to three years and per-chip-family costs that can exceed $50 million before the first silicon ships.
What Does Celera's Platform Actually Do?
The core product is Nesto™, which Celera positions as the first library of digital twins for analog functions. Traditional analog design is largely manual: engineers draw transistor-level circuits by hand, simulate, iterate, and eventually tape out. That process is slow because analog circuits respond to thermal gradients, substrate parasitics, and manufacturing variation in ways digital logic does not.
Nesto replaces handcrafted schematic entry with mathematically exact models of discrete analog building blocks - amplifiers, comparators, voltage regulators, oscillators. The software assembles and optimizes full IC designs from these models, then generates manufacturable layouts. Celera says major customers have validated full-custom analog ICs completed in 10% of the time traditional approaches require. The company has not disclosed which customers or on which process nodes.
What Does $50M in 12 Months Reveal About the Market?
Maverick Silicon returning as the sole Series B funder is unusual. It suggests either that the traction data was compelling enough for the firm to protect its position without bringing in co-investors, or that the round was structured to avoid outside dilution. The concentrated cap table concentrates risk equally.
The analog design automation category has no clear technology incumbent. Synopsys and Cadence Design Systems built the dominant electronic design automation franchises around digital tools, where chip complexity migrated after the 1990s. Analog stayed artisanal. Celera and a small cluster of competitors are now targeting that gap as the AI hardware buildout drives renewed demand for custom analog components - power management, signal conditioning, mixed-signal front ends - that digital chiplets cannot replace.
SiliconGate Acquisition Adds Execution Depth
In June 2026, Celera acquired SiliconGate, a Portugal-based analog design house with offices in Lisbon and Porto and close to two decades of power management work for major global customers. SiliconGate also maintains links to Portuguese universities, providing a talent pipeline at a cost structure well below Silicon Valley rates.
The Series B proceeds are earmarked for growing engineering headcounts in both California and Portugal, and for broadening Nesto's coverage of analog applications. Power management appears to be the first commercial priority.
Why Has Analog Design Automation Stalled Before?
Every serious attempt to automate analog design over the past three decades has run aground at the same point: the physical world diverges from the model. Analog circuits amplify small errors. Automated tools that work cleanly in simulation produce silicon that drifts out of spec on the production floor.
Celera's digital twin approach does not claim to eliminate that divergence. It claims to embed physical sensitivity into the models themselves, so software optimization accounts for variation from the start rather than discovering it at tape-out. That architectural claim has been validated at prototype scale; production scale across multiple nodes and applications is the remaining question. Customers with large analog programs will need to answer it before committing.
Outlook
Celera enters the second half of 2026 with $30 million in fresh capital, an acquired design team on two continents, and customer validation for compressed analog development timelines. Post-money valuation was not disclosed. The near-term test is converting early wins into recurring revenue and demonstrating that Nesto scales beyond power management. Maverick Silicon's willingness to nearly double its previous check at the same concentrated ownership structure implies early commercial data reads well, though independent verification remains limited.
